Transient voltage collapse write assist

Voltage Transients are defined as short duration surges of electrical energy and are the result of the sudden release of energy previously stored or induced by other means, such as heavy inductive loads or lightning. In electrical or electronic circuits, this energy can be released in a predictable manner via controlled switching actions, or randomly induced into a circuit from external sources. Repeatable transients are frequently caused by the operation of motors, generators, or the switching of reactive circuit components. Lightning and ESD generally occur unpredictably, and may require elaborate monitoring to be accurately measured, especially if induced at the circuit board level.

Transient voltage collapse write assist

To take advantage of dynamic data retention, transient voltage collapse (TVC) has been proposed. In this approach, the lowers the bitcell supply below the retention voltage during write operation, hence, eliminating the contention between the pass-gate and the . A transient voltage collapse circuit provides a reference voltage for an SRAM (static random access memory). The SRAM receives a first reference voltage and a second reference voltage higher than the first reference voltage. the low-voltage write margin, a column-based transient voltage collapse (TVC) scheme is employed to weaken the PU transistor during a write [2]. In this work, using pulsed PMOS TVC write assist, complemented by static WLUD, no WLUD and S-WL. The WL voltage level during the first phase of S-WL matches the static.

It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the embodiments. Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures.

It is noted that wherever practicable, similar or like reference numbers may be used in the figures and may indicate similar or like functionality.

The figures depict embodiments for purposes of illustration only.

Publication - Vita Pi-Ho Hu

The cells are arranged as rows and columns, such that each row of cells corresponds to a word. The rows and columns shown in FIG. Each row of the cells representing a word is connected to a word line Each cell is connected to a first reference voltage provided by a transient voltage collapse circuit via a voltage supply line Each cell is also connected to a second reference voltage VDD via a voltage supply line The second reference voltage VDD is higher than the first reference voltage.

Each cell is connected to bit lines and that provide input data to be written in the cell. The data provided at the bit line is complement of the data provided at the bit line In an embodiments, the columns of the SRAM are divided into subsets of columns.

A transient voltage collapse circuit supplies voltage to each subset of the columns. Accordingly, the number of transient voltage collapse circuits matches the number of subsets of columns.

The transient voltage collapse circuit maintains the first reference voltage at a first voltage value V1 that is lower than the second reference voltage VDD when no write operations are performed by SRAM The transient voltage collapse circuit increases the voltage of the first reference voltage during a write operation of the SRAM to a third voltage value V3 that is higher than the first voltage value V1 but lower than the second reference voltage VDD.

The increase in the voltage of the first reference voltage causes decrease in the gap between the first reference voltage V1 and the second reference voltage VDD, thereby enhancing a writing operation of cells according to the data provided as input to the cells via bit lines and The transient voltage collapse circuit comprises a bias transistor T1, a control logica write assist circuitand footer transistors T4 and T5.

The transient voltage collapse circuit generates voltage at the supply terminal and provides the generated voltage to the voltage supply line of the SRAM cells The circuit shown in FIG. Each transistor shown in and FIGS.

The transistors used in the circuit shown in FIG. In some embodiments, the transistors used in the circuits shown in FIGS. Other embodiments can use other types of transistors, for example, BJTs bipolar junction transistors. The control logic has an input terminal N2 and an output terminal N3.Process-circuit co-optimization of transient voltage collapse write assist (TVC-WA) and wordline underdrive read assist (WLUD-RA) features address process variation and fin quantization at 22nm.

A transient voltage collapse circuit provides a reference voltage for an SRAM (static random access memory).

transient voltage collapse write assist

The SRAM receives a first reference voltage and a second reference voltage higher than the first reference voltage. The transient voltage collapse circuit provides the first reference voltage to the SRAM via a voltage supply line.

Transient Voltage Collapse Write Assist (TVC-WA) improves the writability of the SRAM cell by reducing write latency by 44% and Worldline Under Drive Read Assist (WLUD-RA) allows improvement in read stability. Both the circuits allow reduction in the supply voltage . This paper evaluates the impacts of Transient Voltage Collapse (TVC) Write-Assist on the GeOI and SOI FinFET SRAM cells with global and local random variations.

Intel presented several papers on its long-awaited 22nm finfet process at ISSCC , plus one on a low-power x86 core. The firm prefers to call its finfets ‘tri-gate technology’.

“Continuous device width sizing in planar technology is replaced by combining parallel silicon fins to multiply. Abstract: This brief describes a charge redistribution transient cell supply voltage collapse write assist (CR-TVC-WA) for static random access memory.

Although wordline underdrive read assist is a requisite for stable read operations in deep submicrometer technologies, it significantly degrades the write ability.